mvebu: edge → 6.18 LTS family-wide + restore 4 patches lost in #6135#9709
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iav wants to merge 3 commits intoarmbian:mainfrom
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mvebu: edge → 6.18 LTS family-wide + restore 4 patches lost in #6135#9709iav wants to merge 3 commits intoarmbian:mainfrom
iav wants to merge 3 commits intoarmbian:mainfrom
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armbian#9694 split mvebu edge into per-board kernel versions: helios4 on 6.18 LTS, clearfogpro/clearfogbase on 6.15. Both share LINUXCONFIG=linux-mvebu-edge and ARMBIAN_KERNEL_DEB_NAME=mvebu-edge, so building both produced "Duplicate LINUXCONFIG's found!" — two source trees compete for the same package name. Per @igorpecovnik in armbian#9694: "kernel can't be per board". Bump the rest of the mvebu (armhf) family to 6.18 too. mvebu64 and other families are untouched. The mvebu-6.18 patch directory is already in the tree from armbian#9694, so the remaining boards (clearfogpro, clearfogbase) get the same patch set. Affected boards: clearfogpro, helios4, clearfogbase (csc). espressobin and macchiatobin (eos) are mvebu64, not affected. I do not have non-helios4 mvebu hardware; build verified, runtime not. Assisted-by: Claude:claude-opus-4-7
Patch 10-mvebu-clearfog-pcie-updates.patch (Russell King, Nov 2016) was
restored from mvebu-6.6/ to mvebu-6.18/ alongside three other lost
patches. It bundled together two distinct kinds of changes:
1. Functional AER/PME plumbing for the mvebu PCIe controller:
- mvebu_pcie_handle_irq_change() in pci-mvebu.c, which syncs the
hardware PCIE_INT_UNMASK_OFF mask (BIT 8/9/10/16/17/18) with the
emulated bridge config space whenever AER-related bits in
PCI_COMMAND.SERR, BRIDGE_CTL.SERR, DEVCTL.{CERE,NFERE,FERE,URRE}
or RTCTL.{SECEE,SENFEE,SEFEE,PMEIE} change
- Armada 370 erratum: clamp DEVCTL.{URRE,FERE,NFERE,CERE} to 0 in
Root Complex mode
- pci-bridge-emul.c: default bridge->conf.bridgectrl to
PCI_BRIDGE_CTL_SERR (precondition for AER reporting)
2. Two debug hunks: dev_info() probes added during clearfog bring-up:
- drivers/pci/pcie/aspm.c (6 lines): print upstream/downstream ASPM
LNKCAP/LNKCTL on every pcie_aspm_cap_init() call
- drivers/pci/pcie/portdrv.c (2 lines): print PCIe capabilities and
init_service_irqs() return on every port device register
Drop the debug hunks. They were ad-hoc bring-up traces from 2016, never
useful in production, and just noise in dmesg on every boot. The aspm.c
hunk also no longer applies cleanly to 6.18 (function moved from line
617 to 814) — fixing the offset just to keep dev_info() spam is not
worthwhile.
Functional hunks (pci-mvebu.c, pci-bridge-emul.c) keep the original
intent: without them mvebu's hardware AER/PME interrupt masks stay off,
so corrected/uncorrected PCIe errors and PME wake events go undetected
on clearfog boards (NAS use case with NVMe/SATA cards in mPCIe slots).
Mainline still does not have this plumbing — Marek Behún's 2021 rewrite
around pci-bridge-emul did not close this gap.
Assisted-by: Claude:claude-opus-4-7
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📝 WalkthroughWalkthroughThis PR unconditionally sets KERNEL_MAJOR_MINOR="6.18" for all mvebu boards on the edge branch and adds multiple mvebu kernel patches: cpuidle return handling, ClearFog PCIe IRQ masking/forwarding, PCIe Slot Capabilities (SSPL) support, and PCIe bridge emulation dispatch adjustments. Changes
Sequence Diagram(s)sequenceDiagram
participant Guest as PCI config writer
participant BridgeEmul as pci-bridge-emul
participant PCIeCtrl as mvebu PCIe controller
participant HW as PCIe hardware regs
Guest->>BridgeEmul: PCI config write (DEVCTL/RTCTL/SLTCAP/BRIDGECtl)
BridgeEmul->>PCIeCtrl: forward relevant PCIe writes (if has_pcie)
PCIeCtrl->>PCIeCtrl: compute new DEVCTL/RTCTL/SLTCAP values
PCIeCtrl->>PCIeCtrl: determine aer_changed / pme change
alt AER/PME change relevant
PCIeCtrl->>HW: update interrupt unmask registers via mvebu_pcie_handle_irq_change()
end
PCIeCtrl->>HW: write SSPL register on SLTCAP writes
PCIeCtrl-->>BridgeEmul: return success
BridgeEmul-->>Guest: config write acknowledged
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes Possibly related PRs
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05
Compute the relevant PCI_EXP_DEVCTL change mask before clearing the
RC-mode forbidden bits from the local write value. Otherwise a change in
DEVCTL.{CERE,NFERE,FERE} may be missed and the corresponding IRQ mask
update deferred until some later config-space write.
Also restrict the PCI_EXP_RTCTL-triggered IRQ mask update to PMEIE.
mvebu_pcie_handle_irq_change() only uses rootctl.PMEIE, so reacting to
SECEE/SENFEE/SEFEE changes only reruns the helper without affecting the
hardware interrupt mask.
Assisted-by: Claude:claude-opus-4-7
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Thanks for bumping all of edge. If I find the time, I will build and test the clearfog stuff on actual HW. |
igorpecovnik
approved these changes
Apr 22, 2026
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I would say we merge. @Heisath check when you can.
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✅ This PR has been reviewed and approved — all set for merge! |
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Followup to #9694.
This PR bumps the entire mvebu edge branch to 6.18 LTS family-wide.
Restored patches
When bumping the version (commit 1), I checked that the patches in
mvebu-6.18/matched what was previously inmvebu-6.6/. It turned out that in commitf852beca0(PR #6135, "move to archive & cleanup", January 2024), when themvebu-6.6/directory was created, 4 clearfog-family patches were silently dropped:0001-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch10-mvebu-clearfog-pcie-updates.patch11-implement-slot-capabilities-SSPL.patch20-pcie-bridge-emul.patchpci_bridge_emulNeither the commit message, nor the PR #6135 description, nor any of its comments (issue + review) mention dropping these patches — they appear to have fallen out by oversight during a manual cleanup. Restoring them.
Edit applied to one of the patches (commit 2)
10-mvebu-clearfog-pcie-updates.patchby Russell King (Nov 2016) bundled together two distinct kinds of changes:mvebu_pcie_handle_irq_change()syncs the hardwarePCIE_INT_UNMASK_OFFmask of the mvebu PCIe controller with the emulated PCI bridge config (AER bits + PME wake) on writes toPCI_COMMAND.SERR,BRIDGE_CTL.SERR,DEVCTL.{CERE,NFERE,FERE,URRE},RTCTL.{SECEE,SENFEE,SEFEE,PMEIE}. Plus the Armada 370 erratum (clamping DEVCTL bits in RC mode) and a defaultbridge->conf.bridgectrl = PCI_BRIDGE_CTL_SERRinpci-bridge-emul.c.dev_info(...)calls indrivers/pci/pcie/aspm.canddrivers/pci/pcie/portdrv.c— bring-up traces from 2016 that just spam dmesg on every boot. Theaspm.chunk also no longer applies cleanly to 6.18 (function moved from line 617 to 814) — not worth fixing the offset just to keep that spam.Without
10-mvebu-clearfog-pcie-updates.patch, on the mainline 6.18pci-mvebudriver the hardware PCIe error/PME interrupt masks remain disabled — corrected/uncorrected PCIe errors and PME wake events on clearfog boards do not work. This is particularly important for NAS use cases (NVMe/SATA cards in the mPCIe slot). Mainline still hasn't closed this gap (Marek Behún's 2021 rewrite aroundpci-bridge-emuldid not restore this functionality).Affected boards
clearfogpro,helios4,clearfogbase(csc).Verification
./compile.sh kernel ARTIFACT_IGNORE_CACHE=yes BOARD=clearfogpro BRANCH=edge KERNEL_BTF=yes SHARE_LOG=yes USE_CCACHE=yes./compile.sh build BOARD=clearfogpro BRANCH=edge RELEASE=trixie BUILD_DESKTOP=no BUILD_MINIMAL=no KERNEL_CONFIGURE=no KERNEL_BTF=yes USE_CCACHE=yesSummary by CodeRabbit
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